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IRMCF143s 1 www.irf.com ? 20 13 international rectifier submit datasheet feedback n ovember 22, 2013 high performance position servo control ic description IRMCF143s is a high performance flash based motion control ic designed primarily for position servo applications based on an incremental encoder. IRMCF143s is designed to achieve low cost yet high performance control solutions for advanced inverterized servo motor control. IRMCF143s contains two computation engines. one is the flexible motion control engine (mce tm ) for sinusoidal field oriented control (foc) of servo motors ; the other is an 8 - bit high - speed microcontroller (8051). both computation engines are integrated into one monolithic chip. the mce tm contains a collection of control elements implemented in a ded icated computation engine such as proportional plus integral, vector rotator, angle estimator, multiply/divide, and low loss svpwm. the user can program a motion control algorithm by connecting these control elements using a graphic compiler. a unique anal og/digital circuit and algorithm to fully support two leg shunt current sensing is also provided. the 8051 microcontroller performs 2 - cycle instruction execution (15mips at 30mhz 8051clk). the mce and 8051 microcontroller are connected via dual port ram fo r signal monitoring and command input. an advanced graphic compiler for the mce tm is seamlessly integrated into the matlab/simulink environment, while third party jtag - based emulator tools are supported for 8051 software development. IRMCF143s comes in a 6 4 pin qfp package . features ? mce tm (flexible motion control engine) - dedicated computation engine for high efficiency sinusoidal foc control ? built - in ha rdware peripheral for two shunt current feedback reconstruction and analog circuits ? supports incremental encoder with hall effect position sensor initialization ? 24bit posit ion counter ? position capture and compare ? pulse + direction input ? brake control with gatekill input ? loss minimization space vector pwm ? three - channel analog output s (pwm) ? embedded 8 - bit high speed microcontroller (8051) for flexible i/o and man - machine control ? jtag programming port for emulation/debugger ? serial communication interface (uart) ? i2c/spi serial interface ? three general purpose timers, one capture timer ? watchdog timer with independent internal clock ? internal 64 kbyte flash memory ? 5v tolerant i/o ? 3.3v single supply product summary maximum clock input (f crystal ) 60 mhz maximum internal clock (sysclk) 120mhz maximum 8051 clock (8051clk) 30mhz foc computation time 35 sec@100mhz mce tm computation data range 16 bit signed 8051 program flash 52kb 8051 /mce data ram 4kb mce program ram 12kb gatekill latency (digit al filtered) 2 sec pwm carrier frequency 20 bits/ sys clk a/d input channels 8 a/d converter resolution 12 bits a/d converter conversion speed 2 sec analog out put (pwm) resolution 8 bits uart baud rate (typ) 57.6k bps encoder interface 6 number of digital i/o (max) 22 package (lead free) qfp64 ordering information orderable part number package type standard pack form quantity IRMCF143tr lqfp64 tape and reel 2000 IRMCF143ty lqfp64 tray 2000
IRMCF143s 1 www.irf.com ? 20 13 international rectifier submit datasheet feedback n ovember 22, 2013 table of contents 1 overview ................................ ................................ ................................ ................................ .............................. 5 2 pinout ................................ ................................ ................................ ................................ ................................ ... 6 3 IRMCF143s block diagram and main functions ................................ ................................ ................................ 7 4 application connection and pin function ................................ ................................ ................................ .............. 8 4.1 8051 peripheral interface group ................................ ................................ ................................ .................. 9 4.2 motion peripheral interface group ................................ ................................ ................................ ............. 10 4.3 analog interface group ................................ ................................ ................................ .............................. 1 0 4.4 power interface group ................................ ................................ ................................ ............................... 11 4.5 test interface group ................................ ................................ ................................ ................................ .. 11 5 dc characteristics ................................ ................................ ................................ ................................ ............. 11 5.1 absolute maximum ratings ................................ ................................ ................................ ....................... 12 5.2 system clock frequency and power consumption ................................ ................................ .................. 12 5.3 digital i/o dc characteristics ................................ ................................ ................................ .................... 13 5.4 pll and oscillator dc characteristics ................................ ................................ ................................ ....... 14 5.5 analog i/o dc characteristics ................................ ................................ ................................ ................... 14 5.6 under voltage lockout dc characteristics ................................ ................................ ................................ 15 5.7 itrip comparator dc characteristics ................................ ................................ ................................ ........... 15 5.8 cmext and aref characteristics ................................ ................................ ................................ ............ 15 6 ac characteristics ................................ ................................ ................................ ................................ ............. 16 6.1 digital pll ac characteristics ................................ ................................ ................................ ................... 16 6.2 analog to digital converter ac characteristics ................................ ................................ ......................... 17 6.3 op amp ac characteristics ................................ ................................ ................................ ....................... 18 6.4 sync to svpwm and a/d conversion ac timing ................................ ................................ ................... 19 6.5 gatekill to svpwm ac timing ................................ ................................ ................................ ............. 20 6.6 itrip ac timing ................................ ................................ ................................ ................................ ........... 20 6.7 interrupt ac timing ................................ ................................ ................................ ................................ .... 21 6.8 i 2 c ac timing ................................ ................................ ................................ ................................ ............ 22 6.9 spi ac timing ................................ ................................ ................................ ................................ ............ 23 spi write ac timing ................................ ................................ ................................ ................................ ... 23 spi read ac timing ................................ ................................ ................................ ................................ .. 24 6.10 uart ac timing ................................ ................................ ................................ ................................ ....... 25 6.11 capture input ac timing ................................ ................................ ................................ ....................... 26 6.12 jtag ac timing ................................ ................................ ................................ ................................ ........ 27 7 i/o structure ................................ ................................ ................................ ................................ ....................... 28 8 pin list ................................ ................................ ................................ ................................ ................................ 31 9 package dimensions ................................ ................................ ................................ ................................ ......... 33 10 part marking information ................................ ................................ ................................ ................................ .... 34 11 qualification information ? ................................ ................................ ................................ ................................ .. 34
IRMCF143s 3 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year list of tables table 1 . absolute maximum ratings ................................ ................................ ................................ ................... 12 table 2 . system clock frequency ................................ ................................ ................................ ....................... 12 table 3 . digital i/o dc characteristics ................................ ................................ ................................ ................ 13 table 4 . pll dc characteristics ................................ ................................ ................................ ......................... 14 table 5 . analog i/o dc characteristics ................................ ................................ ................................ ............... 14 table 6 . uvcc dc characteristics ................................ ................................ ................................ ....................... 15 table 7 . itrip dc characteristics ................................ ................................ ................................ .......................... 15 table 8 . cmext and aref dc characteristics ................................ ................................ ................................ . 15 table 9 . pll ac characteristics ................................ ................................ ................................ .......................... 16 table 10 . a/d converter ac characteristics ................................ ................................ ................................ ......... 17 table 11 . current sensing op amp ac characteristics ................................ ................................ ....................... 18 table 12 . sync ac characteristics ................................ ................................ ................................ ...................... 19 tabl e 13 . gatekill to svpwm ac timing ................................ ................................ ................................ ......... 20 table 14 . itrip ac timing ................................ ................................ ................................ ................................ ....... 20 table 15 . interrupt ac timing ................................ ................................ ................................ ................................ 21 table 16 . i 2 c ac timing ................................ ................................ ................................ ................................ ........ 22 table 17 . spi write ac timing ................................ ................................ ................................ .............................. 23 table 18 . spi read ac timing ................................ ................................ ................................ .............................. 24 table 19 . uart ac timing ................................ ................................ ................................ ................................ ... 25 table 20 . capture ac timing ................................ ................................ ................................ ............................ 26 table 21 . jtag ac timing ................................ ................................ ................................ ................................ .... 27 table 22 . pin list ................................ ................................ ................................ ................................ ................... 32
IRMCF143s 4 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year list of figures figure 1. typical application block diagram using IRMCF143s ................................ ................................ .............. 5 figure 2. pinout of IRMCF143s ................................ ................................ ................................ ................................ 6 figure 3. IRMCF143s block diagram ................................ ................................ ................................ ....................... 7 figure 4. IRMCF143s application diagram ................................ ................................ ................................ .............. 8 figure 5 . crystal circuit example ................................ ................................ ................................ ............................. 16 figure 6 . voltage droop and s/h hold time ................................ ................................ ................................ ............. 17 figure 7. op amp output capacitor ................................ ................................ ................................ .......................... 18 figure 8 . sync timing ................................ ................................ ................................ ................................ ............. 19 figure 9 . gatekill timing ................................ ................................ ................................ ................................ ........... 20 figure 10 . itrip timing ................................ ................................ ................................ ................................ ............ 20 figure 11 . interrupt timing ................................ ................................ ................................ ................................ ....... 21 figure 12 . i 2 c timing ................................ ................................ ................................ ................................ ............... 22 figure 13 . spi write timing ................................ ................................ ................................ ................................ ...... 23 figure 14 . spi read timing ................................ ................................ ................................ ................................ ....... 24 fi gure 15 . uart timing ................................ ................................ ................................ ................................ ........... 25 figure 16 . capture timing ................................ ................................ ................................ ................................ .... 26 fi gure 17 . jtag timing ................................ ................................ ................................ ................................ ............ 27 figure 18 . pwmul/pwmu h/pwmvl/pwmvh/pwmwl/pwmwh/brake output ................................ .............. 28 figure 19 . all digital i/o except pwm output ................................ ................................ ................................ ........... 28 figure 20 . reset, gatekill i/o ................................ ................................ ................................ .......................... 28 figure 21 . analog input ................................ ................................ ................................ ................................ ........... 29 figure 22. analog operational amplifier output and aref i/o structure ................................ ................................ . 29 figure 23 . vss,avss pin i/o structure ................................ ................................ ................................ ................... 29 figure 24 . vdd1,vddcap pin i/o structure ................................ ................................ ................................ ........... 30 figure 25 . xtal0/xtal1 pins structure ................................ ................................ ................................ .................. 30
IRMCF143s 5 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 1 overview IRMCF143s is a new generation international rectifier integrated circuit device primarily designed as a one - chip solution for complete inverter controlled position servo motor control applications. unlike a traditional microcontroller or dsp, the irmck401 provides a built - in encoder interface and associated field oriented control algorithm using the unique flexible motion control engine (mcetm) for a permanent magnet motor. it contains a flexible 24bit position counter, and separate position capture/compare unit to facilitate indexing function. the mcetm consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port ram to map internal signal nodes. irmck401 also employs additional pwm unit to control a brake igbt . motion control programming is achieved using a dedicated graphical compiler integrated into the matlab/simulinktm development environment. sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 high - s peed 8 - bit microcontroller. the 8051 microcontroller is equipped with a jtag port to facilitate emulation and debugging tools. figure 1 shows a typical application sch ematic using the IRMCF143s . IRMCF143s contains 64k bytes of flash program memory and comes in a 64 - pin qfp package. irmcf 143 s power supply irs 2630 d digial i / o 3 . 3 v passive emi filter host communication motor (pmsm) galvanic isolation eeprom analog input 1 7 6 2 optional encoder opto isolation opto isolation 7 6 figure 1 . typical application block diagram using IRMCF143s
IRMCF143s 6 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 2 pinout 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 15 14 13 16 3 12 4 11 5 6 7 8 9 10 2 1 scl/sdi-sdo sda/cs0 vdd1 vss vddcap p1.3/sync /sck p1.4/enc -a p3.2/int0 34 35 36 33 46 37 45 38 44 43 42 41 40 39 47 48 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ain2 op1o vdcbus p2.7/ao1/mt2 p2.6/ao0 p2.1 p3.7 pwmwh pwmul pwmvl pwmwl pwmuh vss p3.1/ao2 /mt3 ifbuo ifbu- ifbu+ xtal0 hall-2/p3.5/t1 reset p1.5 tck tdi/p5.1 tdo tms/p5.2 p1.2/txd p1.1/rxd pwmvh p3.6 gatekill IRMCF143s (top view) ain4 ain3 ifbvo ifbv+ ifbv- p2.0/dir/nmi p2.2/cap ain1 hall-3/p3.3/int1 p1.7/enc -z p1.6/enc- b p1.0/pulse/t2/mt1 p2.5/int2 brake brakegk xtal1 p2.3/match op1- op1+ vdd1 p3.0/cs1 hall-1/p3.4/t0 vddcap avss aref cmext figure 2 . pinout of IRMCF143s
IRMCF143s 7 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 3 IRMCF143s block diagram and main functions motion control sequencer dual port ram 2kbyte mce program ram 12kbyte program flash 64kb 8bit up address/data bus motion control bus a/d mux s/h d/a (pwm) timer counnter0,1,2 watchdog timer motion control modules uart i2c txd rxd 6 low loss svpwm vbus gatekill to igbt gate drive mini -motion control engine (mini mce) monitoring host interface digital i/os 8bit (8051 ) microcontroller ain1 ain2 jtag emulator debugger 4 freq synthesizer 2 resonator (4mhz) 30mhz ain3 analog input 2 capture interrupt control encoder interface from encoder speed command port 1 scl sda port 2 port 3 ain4 break leg current sensing brake igbt u phase 8bit cpu core local ram 2kbyte 120mhz 3 from hall 3 op1 ifbu ifbv v phase brake gk figure 3 . IRMCF143s block diagram IRMCF143s contains the following functions for ac motor control applications: motion control engine (mce tm ) ? foc (complete field oriented c ontrol) ? proportional plus integral block ? low pass filter ? differentiator and lag (high pass filter) ? ramp ? limit ? angle estimate (sensorless control) ? inverse clark transformation ? vector rotator ? bit latch ? peak detect ? transition ? multiply - divide (signed and unsigned) ? adder ? divide (signed and unsigned) ? subtractor ? comparator ? counter ? accumulator ? switch ? shift ? atan (arc tangent) ? function block (any curve fitting, nonlinear function) ? 16 bit wide logic operations (and, or, xor, not, negate) ? mce tm program memory and dual port ram (6k byte) ? mce tm control sequence
IRMCF143s 1 www.irf.com ? 20 13 international rectifier submit datasheet feedback n ovember 22, 2013 8051 microcontroller ? two 16 bit timer/counters ? one 16 bit periodic timer ? one 16 bit watchdog timer ? one 16 bit capture timer ? up to 2 4 discrete digital i /os ? 8 - channel 12 bit a/d (0 ? 1.2v input) o three b uffered channels , two use for current sensing o five u nbu ffered channels ? jtag port (4 pins) ? up to three channels of analog output (8 bit pwm) ? uart ? i 2 c/spi port ? 64k byte flash memory ? 2k byte data ram 4 application connection and pin function p 1 . 2 / txd p 1 . 1 / rxd p 1 . 3 / sync xtal 0 pwmuh pwmul pwmvh pwmvl pwmwh pwmwl gatekill vbus , ain 1 / 2 / 3 / 4 host microcontroller ( uart ) digital i / o control system clock 4 mhz crystal p 2 . 6 / aopwm 0 analog output xtal 1 p 1 . 5 p 3 . 0 / cs 1 reset t di jtag control ( flash programming & emulation ) t clk t sm t do 0 . 6 v ifbu + ifbu - ifbuo ( 0 - 1 . 2 v ) avdd 1 . 8 v avss vdd 1 3 . 3 v vss cmext brake ifbv + ifbv - ifbvo op 1 + op 1 - op 1 o optional external voltage reference ( 0 . 6 v ) p 2 . 7 / aopwm 1 scl sda other communication ( i 2 c ) frequency synthesizer uart i 2 c / spi port 1 port 2 reset pwm 0 pwm 1 jtag interface low loss space vector pwm break s / h s / h 8051 cpu dual port memory & mce memory ( 6 kb ) motion control modules motion control sequencer 12 bit a / d & mux system clock local ram 2 kbyte program ram ( 32 kbyte ) system reset watchdog timer timer s irmcf 143 s aref pwm 2 p 3 . 1 / aopwm 2 port 3 p 1 . 0 / pulin // t 2 / mt 1 p 2 . 2 / cap p 2 . 0 / puldir / nmi p 2 . 3 / qindex p 2 . 5 / int 2 p 3 . 2 / int 0 5 3 . 3 v encoder 1 . 8 v voltage regulator vddcap 3 . 3 v encoder temperature feedback p 3 . 6 p 3 . 7 p 2 . 1 motor hvic gate drive irs 26 30 d 0 . 6 v encoder interface brakegk figure 4 . IRMCF143s application diagram
IRMCF143s 9 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 4.1 8051 peripheral interface group uart interface p1.2/txd output, transmit data from IRMCF143s p1.1/rxd input, receive data to IRMCF143s discrete i/o interface p1.0/ pulse / t2 /mt1 input/output port 1.0, can be configured as timer/counter 2 input or mce pin t imer 1 output, allocated by mce as pulse input p1.1/rxd input/output port 1.1, can be configured as rxd input p1.2/txd input/output port 1.2, can be configured as txd output p1.3/sync/sck i nput/output port 1.3, can be configured as sync output or spi clock output p1 .4/ enc - a input/output port 1.4 , allocat ed by mce as encoder - a input p1.5 input/output port 1.5 p1.6 /enc - b input/output port 1.6 , allocat ed by mce as encoder - b input p1.7 /enc - z inp ut/output port 1.7, allocat ed by mce as encoder - z input p2.0/ dir/ nmi input/output port 2.0, can be configured as non - maskable interrupt input , allocat ed by mce as direction input p2.1 input/output port 2.1 p2.2 /cap input/output port 2.2 , can be configured as capture timer input p2.3 / match input/output port 2.3 , can be configured as match output p2.5/int2 input/output port 2.5, can be configured as int2 input p2.6/ao 0 input/output port 2.6, can be configured as ao 0 output p2.7/ao 1 /mt2 inp ut/output port 2.7, can be configured as ao 1 output or mce pin t imer 2 output p3.0/ cs1 input/output port 3.0, can be configured as spi chip select 1 p3.1/ao 2 /mt3 input/output port 3.1, can be configured as a o 2 output or mce pin t imer 3 output p3.2/ int0 input/output port 3.2, can be configured as int0 input p 3.3/hall - 3 /int1 input/output port 3.3, can be configured as int1 input, allocat ed by mce as hall - 3 input p3.4/hall - 1 /t0 input /output port 3.4, can be configured as timer 0 input, allocat ed by mce as h all - 1 input p3.5/hall - 2 /t1 input /output port 3.5, can be configured as timer 1 input, allocat ed by mce as hall - 2 input p3.6 input/output port 3.6 p3.7 input/output port 3.7 p5.1/tdi input port 5.1, configured as jtag port by default p5.2/tms input port 5.2 , configured as jtag port by default analog output interface p2.6/ao 0 input/output, can be configured as 8 - bit pwm output 0 with programmable carrier frequency p2.7/ao 1 input/output, can be configured as 8 - bit pwm output 1 with programmable carrier freque ncy p3.1/ao 2 input/output, can be configured as 8 - bit pwm output 2 with programmable carrier frequency crystal interface xtal0 input, connected to crystal xtal1 output, connected to crystal reset interface reset input and output, system reset, doesn?t require external rc time constant i 2 c interface scl/so - si output, i 2 c clock output, or spi data
IRMCF143s 10 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year sda/cs0 input/output, i 2 c data line or spi chip select 0 i 2 c/spi interface scl/so - si output, i 2 c clock output, or spi data sda/cs0 input/output, i 2 c data line or spi chip select 0 p1.3/sync/sck input/output port 1.3, can be configured as sync output or spi clock output p3.0/ cs1 input/output port 3.0, can be configured as spi chip select 1 4.2 motion peripheral interface group pwm pwmuh output, pwm phase u high side gate signal, internally pulled down by 58k?, configured high true at a power up pwmul output, pwm phase u low side gate signal, internally pulled down by 58k?, configured high true at a power up pwmvh output, pwm phase v high side gate signal, intern ally pulled down by 58k?, configured high true at a power up pwmvl output, pwm phase v low side gate signal, internally pulled down by 58k?, configured high true at a power up pwmwh output, pwm phase w high side gate signal, internally pulled down by 58k?, configured high true at a power up pwmwl output, pwm phase w low side gate signal, internally pulled down by 58k?, configured high true at a power up brake output, brake output signal, internally pulled up by 70k?, configured low true at a power up faul t gatekill input, upon assertion this negates all six pwm signals, active low , internally pulled up by 70k? brakegk input, upon assertion, this negates brake signal, active low , internally pulled up by 70k? 4.3 analog interface group avss analog power return, (analog internal 1.8v power is shared with vddcap) aref 0.6v buffered output cmext unbuffered 0.6v, input to the aref buffer, capacitor needs to be connected. op1+ input, operational amplifier positive input for application sensing op1 - input, operationa l amplifier negative input for application sensing op1o output, operational amplifier output for application sensing ifbu + input, operational amplifie r positive input for u phase current sensing ifbu - input, operational amplifie r negative input for u phas e current sensing ifbu o output, operational amplifier output for u phase current sensing ifbv + input, operational amplifie r positive input for v phase current sensing ifbv - input, operational amplifie r negative input for v phase current sensing ifbv o output, operational amplifier outp ut for v phase current sensing vdcbus input, analog input channel (0 ? 1.2v), allocated for dc bus voltage input ain1 input, analog input channel 1 (0 ? 1.2v), allocat ed by mce as speed input, needs to be pulled down to a vss if unused
IRMCF143s 11 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year ain2 input, analog input channel 2 (0 ? 1.2v), allocat ed by mce as torque input, needs to be pulled down to avss if unused ain3 input, analog input channel 3 (0 ? 1.2v), needs to be pulled down to avss if unused ain4 input, analog input channel 4 (0 ? 1.2v), needs to be pulled down to avss if unused 4.4 power interface group vdd1 digital power (3.3v) vddcap internal 1.8v output, requires capacitors to the pin. shared with analog power pad internally note: the internal 1.8v supply is not des igned to power any external circuits or devices. only capacitors should be connected to this pin. vss digital common 4.5 test interface group p5.2/tms jtag test mode input or input digital port tdo jtag data output p5.1/tdi jtag data input, or input digital port tck jtag test clock 4.6 incremental encoder/hall sensor group p1.4/ enc - a incremental encoder a input p1.6/enc - b incremental encoder b input p1.7/enc - z incremental encoder z input p3.3/hall - 3 /int1 hall sensor 3 input p3.4/hall - 1 /t0 hall sensor 1 input p3.5/hall - 2 /t1 hall sensor 2 input
IRMCF143s 12 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 5 dc characteristics 5.1 absolute maximum ratings symbol parameter min typ max condition v dd1 supply voltage - 0.3 v - 3.6 v respect to vss v ia analog input voltage - 0.3 v - 1.98 v respect to avss v id digital input voltage - 0.3 v - 6.0 v respect to vss t a ambient temperature - 40 ?c - 85 ?c t s storage temperature - 65 ?c - 150 ?c table 1 . absolute maximum ratings caution: stresses beyond those listed in ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specif ications are not implied. 5.2 system clock frequency and power consumption c aref = 1nf, c mext = 100nf. vdd1=3.3v, unless specified, ta = 25?c. symbol parameter min typ max unit sysclk system clock 32 - 1 2 0 mhz p d power consumption 1 0 0 1) - mw table 2 . system clock frequency note 1) the value is based on the condition of mce clock=1 0 0mhz, 8051 clock 20 mhz with a actual motor running by a typical mce application program and 8051 code.
IRMCF143s 13 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 5.3 digital i/o dc characteristics symbol parameter min typ max condition v dd1 supply voltage 3.0 v 3.3 v 3.6 v recommended v il input low voltage - 0.3 v - 0.8 v recommended v ih input high voltage 2.0 v 3.6 v recommended c in input capacitance - 3.6 pf - (1) i l input leakage current 10 na 1 a v o = 3.3 v or 0 v i ol1 (2) low level output current 8.9 ma 13.2 ma 15.2 ma v ol = 0.4 v (1) i oh1 (2) high level output current 12.4 ma 24.8 ma 38 ma v oh = 2.4 v (1) i ol2 (3) low level output current 17.9 ma 26.3 ma 33.4 ma v ol = 0.4 v (1) i oh2 (3) high level output current 24.6 ma 49.5 ma 81 ma v oh = 2.4 v (1) table 3 . digital i/o dc characteristics note: (1) data guaranteed by design. (2) applied to scl/so - si, sda/cs0 pins. (3) applied to all digital i/o pins except scl/so - si and sda/cs0 pins.
IRMCF143s 14 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 5.4 pll and oscillator dc characteristics c aref = 1nf, c mext = 100nf. vdd1=3.3v, unless specified, ta = 25?c. symbol parameter min typ max condition v il osc oscillator (xtal0,1) input low voltage 0 - 0.2* v ddcap v ddcap = voltage at vddcap pin v ih osc oscillator (xtal0,1) input high voltage 0.8* v ddcap - v ddcap v ddcap = voltage at vddcap pin table 4 pll dc characteristics 5.5 analog i/o dc c haracteristics - op amp s for application sensing ( op1 +, op1 - , op1 o , op2 +, op2 - , op2 o, op3 +, op3 - , op3 o) c aref = 1nf, c mext = 100nf. vdd1=3.3v, unless specified, ta = 25?c. symbol parameter min typ max condition v offset input offset voltage - - 26 mv v avdd = 1.8 v v i input voltage range 0 v 1.2 v recommended v outsw op amp output operating range 50 mv (1) - 1.2 v v avdd = 1.8 v c in input capacitance - 3.6 pf - (1) r fdbk op amp feedback resistor 5 k ? - 20 k ? requested between ifbo and ifb - op gaincl operating close loop gain 80 db - - (1) cmrr common mode rejection ratio - 80 db - (1) i src op amp output source current - 1 ma - v out = 0.6 v (1) i snk op amp output sink current - 100 a - v out = 0.6 v (1) table 5 . analog i/o dc characteristics note: (1) data guaranteed by design.
IRMCF143s 15 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 5.6 under voltage lockout dc characteristics unless specified, ta = 25?c. symbol parameter min typ max condition uv cc+ uvcc positive going threshold 2.78 v 3.04 v 3. 2 3 v (1) uv cc- uvcc negative going threshold 2.78 v 2.97 v 3. 2 3 v uv cc h uvcc hysteresys - 73 mv - (1) table 6 . uvcc dc characteristics note: (1) data guaranteed by design. 5.7 itrip comparator dc characteristics unless specified, vdd1=3.3v, ta = 25?c. symbol parameter min typ max condition itrip + itrip positive going threshold - 1.22v - v dd1 = 3.3 v itrip - itrip negative going threshold - 1.10v - v dd1 = 3.3 v itriph itrip hysteresys - 120mv - table 7 . itrip dc characteristics 5.8 cmext and aref chara cteristics c aref = 1nf, c mext = 100nf. unless specified, ta = 25?c. symbol parameter min typ max condition v cm cmext voltage 495 mv 600 mv 700 mv v vdd 1 = 3.3 v v aref buffer output voltage 495 mv 600 mv 700 mv v vdd 1 = 3.3 v ? v o load regulation (v dc - 0.6) - 1 mv - (1) psrr power supply rejection ratio - 75 db - (1) table 8 . cmext and aref dc characteristics note: (1) data guaranteed by design.
IRMCF143s 16 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 6 ac c haracteristics 6.1 digital pll ac c haracteristics symbol parameter min typ max condition f clkin crystal input frequency 3.2 mhz 4 mhz 60 mhz (1) (see figure below) f pll internal clock frequency 32 mhz 50 mhz 128 mhz (1) f lwpw sleep mode output frequency f clkin 256 - - (1) j s short time jitter - 200 psec - (1) d duty cycle - 50 % - (1) t lock pll lock time - - 500 sec (1) table 9 . pll ac characteristics note: (1) data guaranteed by design. xtal r 1 =1m r 2 =10 c 1 = 15 pf c 2 = 15 pf figure 5 . crystal circuit example
IRMCF143s 17 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 6.2 analog to digital converter ac c haracteristics unless specified, ta = 25?c. symbol parameter min typ max condition t conv conversion time - - 2.05 sec (1) t hold sample/hold maximum hold time - - 10 sec voltage droop 15 lsb (see figure below) table 10 . a/d converter ac characteristics note: (1) data guaranteed by design. t h o l d v o l t a g e d r o o p t s a m p l e s / h v o l t a g e i n p u t v o l t a g e figure 6 . voltage droop and s/h hold time
IRMCF143s 18 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 6.3 op amp ac c haracteristics unless specified, ta = 25?c. symbol parameter min typ max condition op sr op amp slew rate - 10 v/sec - vdd1 = 3.3 v, cl = 33 pf (1) op imp op input impedance - 10 8 - (1) (2) t set settling time - 400 ns - vdd1 = 3.3 v, cl = 33 pf (1) table 11 current sensing op amp ac characteristics note: (1) data guaranteed by design. (2) to guarantee stability of the operational amplifier, it is recommended to load the output pin by a capacitor of 47pf, see figure 7 . avref external components 47pf figure 7 . op amp output capacitor
IRMCF143s 19 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 6.4 sync to svpwm and a/d conversion ac t iming sync iu,iv,iw t wsync t dsync1 ainx t dsync2 pwmux,pwmvx,pwmwx t dsync3 figure 8 . sync timing unless specified, ta = 25?c. symbol parameter min typ max unit t wsync sync pulse width - 32 - sysclk t dsync1 sync to current feedback conversion time - - 100 sysclk t dsync2 sync to ain0 - ain 4 analog input conversion time - - 200 sysclk (1) t dsync3 sync to pwm output delay time - - 2 sysclk table 12. sync ac characteristics note: (1) ain 3 , ain4 and op1o channels are converted once every 3 sync events
IRMCF143s 20 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 6.5 gatekill to svpwm ac t iming gatekill pwmux , pwmvx , pwmwx t w gk t d gk figure 9 . gatekill timing unless specified, ta = 25?c. symbol parameter min typ max unit t wgk gatekill pulse width 32 - - sysclk t dgk gatekill to pwm output delay - - 100 sysclk table 13. gatekill to svpwm ac timing 6.6 itrip ac t iming itrip pwmuh,pwmul, pwmvh,pwmvh, pwmwh,pwmwl t itrip figure 10 . itrip timing unless specified, ta = 25?c. symbol parameter min typ max unit t itrip itrip propagation delay - - 100(sysclk)+1.0usec sysclk+usec table 14. itrip ac timing
IRMCF143s 21 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 6.7 i nterrupt ac t iming p3.2/int0 p3.3/int1 internal program counter internal vector fetch t wint t dint figure 11 . interrupt timing unless specified, ta = 25?c. symbol parameter min typ max unit t wint int0, int1 interrupt assertion time 4 - - sysclk t dint int0, int1 latency - - 4 sysclk table 15. interrupt ac timing
IRMCF143s 22 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 6.8 i 2 c ac t iming scl sda t i 2 st 1 t i 2 st 2 t i 2 wsetup t i 2 clk t i 2 whold t i 2 rsetup t i 2 rhold t i 2 clk t i 2 en 1 t i 2 en 2 figure 12 . i 2 c timing unless specified, ta = 25?c. symbol parameter min typ max unit t i2clk i 2 c clock period 10 - 8192 sysclk t i2st1 i 2 c sda start time 0.25 - - t i2clk t i2st2 i 2 c scl start time 0.25 - - t i2clk t i2wsetup i 2 c write setup time 0.25 - - t i2clk t i2whold i 2 c write hold time 0.25 - - t i2clk t i2rsetup i 2 c read setup time i 2 c filter time (1) - - sysclk t i2rhold i 2 c read hold time 1 - - sysclk table 16. i 2 c ac timing note: (1) i 2 c read setup time is determined by the programmable filter time applied to i 2 c communication.
IRMCF143s 23 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 6.9 spi ac timing spi write ac timing p 1 . 3 / sync / sck scl / s o - s i t spiclk t wrdelay t cshold sda / cs 0 p 3 . 0 / int 2 / cs 1 t cshigh bit 7 ( msb ) bit 0 ( lsb ) t spiclkht t spiclklt t csdelay figure 13 . spi write timing unless specified, ta = 25?c. symbol parameter min typ max unit t spiclk spi clock period 4 - - sysclk t spiclkht spi clock high time - 1/2 - t spiclk t spiclklt spi clock low time - 1/2 - t spiclk t csdelay cs to data delay time - - 10 nsec t wrdelay clk falling edge to data delay time - - 10 nsec t cshigh cs high time between two consecutive byte transfer 1 - - t spiclk t cshold cs hold time - 1 - t spiclk table 17. spi write ac timing
IRMCF143s 24 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year spi read ac timing p 1 . 3 / sync / sck scl / s o - s i t spiclk t rdsu t cshold sda / cs 0 p 3 . 0 / int 2 / cs 1 t cshigh bit 7 ( msb ) bit 0 ( lsb ) t spiclkht t spiclklt t csrd t rdhold figure 14 . spi read timing unless specified, ta = 25?c. symbol parameter min typ max unit t spiclk spi clock period 4 - - sysclk t spiclkht spi clock high time - 1/2 - t spiclk t spiclklt spi clock low time - 1/2 - t spiclk t csrd cs to data delay time - - 10 nsec t rdsu spi read data setup time 10 - - nsec t rdhold spi read data hold time 10 - - nsec t cshigh cs high time between two consecutive byte transfer 1 - - t spiclk t cshold cs hold time - 1 - t spiclk table 18. spi read ac timing
IRMCF143s 25 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 6.10 uart ac t iming txd rxd data and parity bit start bit t baud stop bit t uartfil figure 15 . uart timing unless specified, ta = 25?c. symbol parameter min typ max unit t baud baud rate period - 57600 - bit/sec t uartfil uart sampling filter period (1) - 1/16 - t baud table 19. uart ac timing note: (1) each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/16 t baud . if three sampled values do not agree, then uart noise error is generated.
IRMCF143s 26 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 6.11 capture i nput ac t iming p 1 . 4 / cap crev ( h , l ) internal register t caphigh t capclk t crdelay t caplow t cldelay clast ( h , l ) internal register t intdelay interrupt vector fetch interrupt figure 1 6 . capture timing unless specified, ta = 25?c. symbol parameter min typ max unit t capclk capture input period 8 - - sysclk t caphigh capture input high time 4 - - sysclk t caplow capture input low time 4 - - sysclk t crdelay capture falling edge to capture register latch time - - 4 sysclk t cldelay capture rising edge to capture register latch time - - 4 sysclk t intdelay capture input interrupt latency time - - 4 sysclk table 20 . capture ac timing
IRMCF143s 2 7 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 6.12 jtag ac t iming tck tdo t jhigh t jclk t co t jlow t jsetup t jhold tdi / tms figure 17 . jtag timing unless specified, ta = 25?c. symbol parameter min typ max unit t jclk tck period - - 50 mhz t jhigh tck high period 10 - - nsec t jlow tck low period 10 - - nsec t co tck to tdo propagation delay time 0 - 5 nsec t jsetup tdi/tms setup time 4 - - nsec t jhold tdi/tms hold time 0 - - nsec table 21. jtag ac timing
IRMCF143s 28 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 7 i/o structure the following figure shows the pwm output (pwmuh/pwmul/pwmvh/pwmvl/pwmwh/pwmwl / brake ) 270 ? 6.0v 6.0v internal digital circuit high true logic vdd1 (3.3v) vss 58k ? pin figure 18 . pwmul/pwmuh/pwmvl/pwmvh/pwmwl/pwmwh / brake output the following figure shows the digital i/o structure except the pwm output 6.0v 6.0v internal digital circuit low true logic vdd1 (3.3v) 70k ? pin vss 270 ? figure 19 . all digital i/o except pwm /brake output the following figure shows reset and gatekill i/o structure. 270 ? 6.0v 6.0v reset gatekill circuit vdd1 (3.3v) 70k ? pin vss figure 20 . reset, gatekill i/o
IRMCF143s 29 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year the following figure shows the analog input structure . 1 ? 6 . 0 v 6 . 0 v analog input pin avss analog circuit vddcap ( 1 . 8 v ) figure 21 . analog input the following figure shows all analog operational amplifier output pins and aref pin i/o structure. 6.0v 6.0v analog output pin avss analog circuit vddcap(1.8v) figure 22. analog operational amplifier output and aref i/o structure the following figure shows the vss,avss pin i/o structure pin vdd 1 avdd 6 . 0 v figure 23 . vss,avss pin i/o structure
IRMCF143s 30 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year the following figure shows the vdd1,vddcap pin i/o structure pin vss 6 . 0 v figure 24 . vdd1,vddcap pin i/o structure the following figure shows the xta l0 and xtal1 pins structure 1 ? 6 . 0 v 6 . 0 v pin vss vddcap ( 1 . 8 v ) figure 25 . xtal0/xtal1 pins structure
IRMCF143s 31 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 8 pin list pin number pin name internal pull - up / down pin type description 1 xtal0 -- i crystal input 2 xtal1 -- o crystal output 3 p1.0/ pulse / t2 /mt 1 -- i/o discrete programmable i/o or pulse input or timer/counter 2 input or mce pin timer 1 4 scl/so - si -- i/o i 2 c clock output (open drain, need pull up) or spi data 5 sda/cs0 -- i/o i 2 c data (open drain, need pull up) or spi chip select 0 6 p1.3/sync/sck -- i/o discrete programmable i/o or sync output or spi clock output 7 p1.4/enc - a -- i/o discrete program mable i/o or encoder a input 8 p1.6 /enc - b -- i/o discrete programmable i/o or encoder b input 9 p1.7 /enc - c -- i/o discrete programmable i/o or encoder c input 10 vdd1 -- p 3.3v digital power 11 vss -- p digital common 12 vddcap -- p internal 1.8v output, capacitor(s) to be connected 13 p2.0/ dir/ nmi -- i/o discrete programmable i/o or dir input or non - maskable interrupt input 14 p3.2/int0 -- i/o discrete programmable i/o or interrupt 0 input 15 p2.2 /cap -- i/o discrete programmable i/o or capture timer input 16 p2.3 / match -- i/o discrete programmable i/o or match output 17 p2.5/int2 -- i/o discrete programmable i/o or interrupt 2 input 18 p2.6/ao 0 -- i/o discrete programmable i/o or pwm 0 digital output 19 p2.7/ao 1 /mt2 -- i/o discrete programmable i/o or pwm 1 digital output or mce pin timer 2 output 20 op1o -- o op amp output for application sensing , 0 - 1.2v range 21 op1 - -- i op amp negative input for application sensing , 0 - 1.2v range, needs to be pulled down to avss if unused 22 op1+ -- i op amp positive input for application sensing , 0 - 1.2v range, needs to be pulled down to avss if unused 23 vdcbus -- i analog input channel (0 ? 1.2v), allocated by mce for dc bus voltage input 24 ain1 -- i analog input channel 1, 0 - 1.2v range, allocate d by mce as speed input, needs to be pulled down to avss if unused 25 ain2 -- i analog input channel 2, 0 - 1.2v range, allocate d by mce as torque input, needs to be pulled down to avss if unused 26 ain3 -- i analog input channel 3, 0 - 1.2v range, needs to be pulled down to avss if unused 27 ain4 -- i analog input channel 4, 0 - 1.2v range, needs to be pulled down to avss if unused 28 ifbu - -- i op amp negative input for u phase current sensing , 0 - 1.2v range 29 ifbu + -- i op amp positive input for u phase current sensing , 0 - 1.2v range 30 ifbu o -- o op amp output for u phase current sensing , 0 - 1.2v range
IRMCF143s 32 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year pin number pin name internal pull - up / down pin type description 31 cmext -- o unbuffered 0.6v output. capacitor needs to be connected. 32 aref -- o analog reference voltage output (0.6v) 3 3 ifbv - -- i op amp negative input for v phase current sensing , 0 - 1.2v range 34 ifbv + -- i op amp positive input for v phase current sensing , 0 - 1.2v range 35 ifbv o -- o op amp output for v phase current sensing , 0 - 1.2v range 36 avss -- p analog common 37 vddcap -- p internal 1.8v output, capacitor(s) to be connected 38 vdd1 -- p 3.3v digital power 39 vss -- p digital common 40 p3.1/ao 2 /mt3 -- i/o discrete programmable i/o or pwm 2 digital output or mce pin timer 3 output 41 pwmwl 58 k pull down o pwm gate drive for phase w low side, configurable either high or low true. 42 pwmvl 58 k pull down o pwm gate drive for phase v low side, configurable either high or low true 43 pwmul 58 k pull down o pwm gate drive for phase u low side, configurable either high or low true 44 pwmwh 58 k pull down o pwm gate drive for phase w high side, configurable either high or low true 45 p3.7 -- i/o discrete programmable i/o 46 p2.1 -- i/o discrete programmable i/o 47 p3.6 -- i/o discrete programmable i/o 48 pwmvh 58 k pull down o pwm gate drive for phase v high side, configurable either high or low true 49 pwmuh 58 k pull down o pwm gate drive for phase u high side, configurable either high or low true 50 p1.5 i/o discrete programmable i/o. 51 brake 70 k pull up o brake output , configured low true at a power up 52 brakegk 70 k pull up i brake shutdown input, active low input. 53 gatekill 70 k pull up i pwm shutdown input, configurable digital filter, active low input. 54 p3.0/ cs1 70 k pull up i/o discrete programmable i/o or spi chip select 1 55 tms / p5.2 -- i jtag test mode select or digital input port 56 tdo -- o jtag test data output 57 tdi / p5.1 -- i jtag test data input or digital input port 58 tck -- i jtag test clock 59 reset -- i reset, low true, schmitt trigger input 60 p1.1/rxd -- i/o uart receiver input or discrete programmable i/o 61 p1. 2 / t xd -- i/o uart transmitter output or discrete programmable i/o 62 hall - 1/ p3.4/t0 -- i/o hall - 1 input or d iscrete pro grammable i/o or timer/counter 0 input 63 hall - 2/ p3.5/t1 -- i/o hall - 2 input or d iscrete pro grammable i/o or timer/counter 1 input 64 hall - 3/ p3.3/int1 -- i/o hall - 3 input or discrete programmable i/o or in terrupt 1 input table 22 . pin list
IRMCF143s 33 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 9 package dimensions
IRMCF143s 34 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year 10 part marking information irmcf 143 ywwp xxxxxx ir logo production lot date code part number pin 1 indentifier 11 qualification information ? qualification level industrial ?? (per jedec jesd 47e) moisture sensitivity level msl3 ??? (per ipc/jedec j - std - 020c) esd machine model class b (per jedec standard jesd22 - a114d) human body model class 2 (per eia/jedec standard eia/jesd22 - a115 - a) rohs compliant yes ? qualification standards can be found at international rectifier?s web site http://www.irf.com/ ?? higher qualification ratings may be available should the user have such requirements. please contact your international rectifier sales representative for further information. ??? higher msl ratings may be available for the specific package types listed here. please contact your international rectifier sales representative for further information. note: test condition for temperature cycling test is - 40c to 125c.
IRMCF143s 35 www.irf.com ? 20 13 international rectifier submit datasheet feedback month xx , year revision history rev a ( november 22 , 201 3 ) first revision data and specifications are subject to change without notice ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 - 7105 tac fax: (310) 252 - 7903 visit us at www.irf.com for sales contact information

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